Issue #2354 - Restore ARM32 buildability on Linux.

Fix ION breakages due to BigInt changes.
Fix breakages from libjpeg, libyuv and libvpx upgrades.
Restore ARM(32/64) NEON FPU support in libyuv.

3 files changed, 13 insertions, 20 deletions

diff --git a/js/src/jit/arm/CodeGenerator-arm.h b/js/src/jit/arm/CodeGenerator-arm.h
index 02fc40cb26..388ec23df7 100644
--- a/js/src/jit/arm/CodeGenerator-arm.h
+++ b/js/src/jit/arm/CodeGenerator-arm.h
@@ -288,24 +288,6 @@ class CodeGeneratorARM : public CodeGeneratorShared
     void visitUDiv(LUDiv* ins);
     void visitUMod(LUMod* ins);
     void visitSoftUDivOrMod(LSoftUDivOrMod* ins);
-
-  public:
-    // Unimplemented SIMD instructions
-    void visitSimdSplatX4(LSimdSplatX4* lir) { MOZ_CRASH("NYI"); }
-    void visitSimd128Int(LSimd128Int* ins) { MOZ_CRASH("NYI"); }
-    void visitSimd128Float(LSimd128Float* ins) { MOZ_CRASH("NYI"); }
-    void visitSimdReinterpretCast(LSimdReinterpretCast* ins) { MOZ_CRASH("NYI"); }
-    void visitSimdExtractElementI(LSimdExtractElementI* ins) { MOZ_CRASH("NYI"); }
-    void visitSimdExtractElementF(LSimdExtractElementF* ins) { MOZ_CRASH("NYI"); }
-    void visitSimdGeneralShuffleI(LSimdGeneralShuffleI* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdGeneralShuffleF(LSimdGeneralShuffleF* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdSwizzleI(LSimdSwizzleI* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdSwizzleF(LSimdSwizzleF* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdBinaryCompIx4(LSimdBinaryCompIx4* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdBinaryCompFx4(LSimdBinaryCompFx4* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdBinaryArithIx4(LSimdBinaryArithIx4* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdBinaryArithFx4(LSimdBinaryArithFx4* lir) { MOZ_CRASH("NYI"); }
-    void visitSimdBinaryBitwise(LSimdBinaryBitwise* lir) { MOZ_CRASH("NYI"); }
 };
 
 typedef CodeGeneratorARM CodeGeneratorSpecific;
diff --git a/js/src/jit/arm/MacroAssembler-arm.cpp b/js/src/jit/arm/MacroAssembler-arm.cpp
index e099022c27..cf00f12fb6 100644
--- a/js/src/jit/arm/MacroAssembler-arm.cpp
+++ b/js/src/jit/arm/MacroAssembler-arm.cpp
@@ -3013,7 +3013,7 @@ MacroAssemblerARMCompat::testInt32(Condition cond, const BaseIndex& src)
     return cond;
 }
 
-+Assembler::Condition
+Assembler::Condition
 MacroAssemblerARMCompat::testBigInt(Condition cond,const BaseIndex& src)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
@@ -3766,7 +3766,7 @@ MacroAssemblerARMCompat::testStringTruthy(bool truthy, const ValueOperand& value
     return truthy ? Assembler::NotEqual : Assembler::Equal;
 }
 
-+Assembler::Condition
+Assembler::Condition
 MacroAssemblerARMCompat::testBigIntTruthy(bool truthy, const ValueOperand& value)
 {
     Register bi = value.payloadReg();
diff --git a/js/src/jit/arm/SharedIC-arm.cpp b/js/src/jit/arm/SharedIC-arm.cpp
index f3f907250f..c6353d6a32 100644
--- a/js/src/jit/arm/SharedIC-arm.cpp
+++ b/js/src/jit/arm/SharedIC-arm.cpp
@@ -201,6 +201,17 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
         // Compile -x as 0 - x.
         masm.as_rsb(R0.payloadReg(), R0.payloadReg(), Imm8(0));
         break;
+      case JSOP_INC: {
+        RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
+        masm.inc32(&rval);
+        break;
+      }
+      case JSOP_DEC: {
+        RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
+        masm.dec32(&rval);
+        break;
+      }
+
       default:
         MOZ_CRASH("Unexpected op");
     }