| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | development/yosys: Added (A framework for Verilog RTL synthesis) | William PC | 2022-11-05 |
| Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> | |||
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index : slackbuilds | |
| slackbuilds.org: master branch [Local Fork] | khronosschoty@posteo.org |
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