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| author | William PC <w_calandrini[at]hotmail[dot]com> | 2022-11-05 05:36:42 +0000 |
|---|---|---|
| committer | Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2022-11-05 21:15:11 +0700 |
| commit | 66f5af0cd3942d3d7779d407fcebad4a0a2759be (patch) | |
| tree | bbf8b21dcc15cae1ba598d9b01663653f931109f /development/yosys/yosys.info | |
| parent | a1d641657f265660dcdbfae2375aed2317dad80e (diff) | |
| download | slackbuilds-66f5af0cd3942d3d7779d407fcebad4a0a2759be.tar.gz | |
development/yosys: Added (A framework for Verilog RTL synthesis)
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'development/yosys/yosys.info')
| -rw-r--r-- | development/yosys/yosys.info | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/development/yosys/yosys.info b/development/yosys/yosys.info new file mode 100644 index 0000000000..89b45ecc9d --- /dev/null +++ b/development/yosys/yosys.info @@ -0,0 +1,10 @@ +PRGNAM="yosys" +VERSION="0.22" +HOMEPAGE="https://yosyshq.net/yosys" +DOWNLOAD="https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.22.tar.gz" +MD5SUM="6c5ce0aa586019ec88ebfdae122157aa" +DOWNLOAD_x86_64="" +MD5SUM_x86_64="" +REQUIRES="" +MAINTAINER="William PC" +EMAIL="w_calandrini[at]hotmail[dot]com" |