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diff --git a/development/yosys/README b/development/yosys/README new file mode 100644 index 0000000000..5913646914 --- /dev/null +++ b/development/yosys/README @@ -0,0 +1,22 @@ + Yosys is a framework for Verilog RTL synthesis. It currently has +extensive Verilog-2005 support and provides a basic set of synthesis +algorithms for various application domains. + + Yosys can be adapted to perform any synthesis job by combining the +existing passes (algorithms) using synthesis scripts and adding +additional passes as needed by extending the yosys C++ code base. + + Yosys is free software licensed under the ISC license (a GPL +compatible license that is similar in terms to the MIT license or +the 2-clause BSD license). + + + By default it compiles using gcc if you want to use clang set +the environment variable CLANG=yes. + If you want to enable GHDL set GHDL=yes, this requires the GHDL +package. + For enabling protobuf install protobuf3 and set PROTOBUF=yes. + For building the python wrappers set PYTHON=yes. + If you want to enable ABC for synthesis and verification of +binary sequential logic circuits set ABCEXTERNAL=yes, this +requires berkeley-abc package. |